Electronic devices and systems often represent information by varying electrical parameters such as voltage, current, frequency, wavelength, etc. These electrical parameters may be controlled in many ways, for example, a digital device may vary a voltage amplitude discretely over time while an analog device may vary a voltage amplitude continuously over time. These two variations alone provide limitless ways to represent information.
Digital devices are further differentiated as synchronous or asynchronous. Synchronous devices use periodic synchronization signals, also called clock pulses, to synchronize device circuitry while asynchronous devices are not slaved to a clock. Synchronous signaling is typically less complex and has less overhead than asynchronous signaling, which benefits device performance.
Unfortunately, synchronous devices and systems are susceptible to errors within their clock signals. Ideally, a synchronous system has universal clock signal characteristics such as phase or frequency throughout the entire system. In practice this is not achieved. Some potential sources of error are environmental influences on clocking, clock distribution variations, and signaling between clock domains.
In devices or systems that are synchronized with a clock signal, slight variations in the clock signal often cause malfunctions. If a signal is sampled at a wrong time, data corruption occurs. For example, metastability happens if a data signal transitions too close to or at the same time as a clock transition, therefore causing the data signal to be sampled in an invalid intermediate state. Therefore, in order to reliably sample a data value it must be steady for a brief time before a clock transition through a brief time after a clock transition, also called setup time and hold time, respectively.
When signals are passed between clock domains, from circuitry running on one clock to circuitry running on another clock, asynchronous relationships at the clock domain interface must be reconciled to ensure data integrity. Since each domain is operating on different clocks, numerous sources for error exist. For example, clock domain interfaces may have an unknown phase relationship even if the two clock domains are operating at the same frequency. Therefore data corruption is likely if not otherwise compensated for.
Some architectures have multiple lanes crossing clock domain interfaces, where each lane includes its own data interface, for example, an M-bit interface. These multiple lanes may be in a channel that has the same sending clock and the same receiving clock. Even if multiple lanes crossing between clock domains each can compensate for the asynchronous interface, they may still lose cycle coherency between the lanes, where cycle coherency involves the data across all interfaces releasing in the same sending clock cycle and being captured in the same receiving clock cycle.